1. Field of the Invention
The present invention relates to the field of microelectronics, and in particular to digital circuits. Still more particularly, the present invention relates to digital counters.
2. Description of the Prior Art
In digital circuit designs, digital counter circuits are often used to control the timing and/or sequencing of operations which occur in other portions of an overall circuit design. In many circuit designs, it is desirable to use a digital counter circuit having N-number of outputs, wherein only one of the N outputs is active at any instance. Since the outputs of the counter may be used to control operations in other portions of the circuit, and such operations may not be able to occur at the same time, it may be critical that no more than one output of the counter is active at any time, and that no false states occur during transitions, including the period during power-up.
One such counter circuit is implemented by clocking a single bit through a series of sequentially connected latches connected in a shift register configuration. This type of counter may be referred to as a "ring counter", and is sometimes referred to as a shift register counter. One advantage of the ring counter is that decoding logic is not required to determine which one of the N outputs should be active during a particular clock cycle. If decoding logic is used to activate one of the N outputs, as in a "Johnson counter," glitches may be generated as the decode logic settles and reaches a final state, thereby causing glitches on the output, where more than one output is active at a particular instance.
Although ring counters have the advantages mentioned above, ring counters also have disadvantages. One disadvantage is the possibility that the shift register chain may enter into an improper state. An improper state occurs in a ring counter when more than one active bit enters the shift register chain, which causes more than one output to be active. If, for example, during power-up, the counter does not reset properly, such an improper state may occur. In other cases, such as transitory conditions caused by power supply transients, an improper state can occur. Moreover, once a ring counter has entered into an improper state, such an improper state will continue until a reset signal is received, which will clear all but one active output.
Therefore, it would be desirable to have an apparatus to prevent a ring counter from outputting an improper state in the form of having more than one output in the active state at a particular instance.